The present invention is directed to a circuit for synchronizing an asynchronous input with a two-clock MOS system with particular utility in large scale integrated circuitry.
In conventional clocked ratio MOS digital systems, signal transition is only permitted within certain time intervals of the two-phase system. However, with an asynchronous input, transition may take place at any time, and it has been discovered that inherent difficulties result from the basic structure used in clocked ratio MOS logic should the input signal change close to the termination of a clock period.
In the prior logic circuits, a full and usable output level may not be developed when an input transition takes place near the trailing edge of a clock pulse. This phenomenon, when occuring, causes ambiguity in the logical state of a digital integrated circuit.